The present invention relates to a bypass capacitor attached to the top of an integrated circuit chip and/or a tape-automated-bonding (TAB) tape, as well as a method of TAB manufacturing in which the capacitor electrodes are positioned adjacent to the power and ground pads on the integrated circuit chip. The use of short spaced multiple wire bonded leads between the capacitor and the chip reduce the interconnect inductance.
When a large number of circuits switch simultaneously, a current surge is generated and is accompanied by an AC voltage noise throughout a power distribution network. This phenomenon causes rise time degradation and may cause false switching of logic gates. The common practice to resolve the power disturbed noise in fast switching applications is to incorporate chip capacitors either on the single chip package or on the printed circuit board. However, there are two factors that limit the application of standard practices in high speed applications: the interconnect inductance and the capacitor self-inductance. While a larger area capacitor with thinner separation between the electrodes reduces the self-inductance of the capacitor, the length of the interconnections still remains a problem. The switching noise is linearly proportional to the magnitude of the current and inversely proportional to the signal edge rates. The inductance of the interconnect between the capacitors and the chip becomes an appreciable source of noise. The finite inductance of an interconnect, such as 0.100 inch wire bond leads plus the trace length could be high enough that make the capacitor ineffective in suppressing the switching noise.
The present invention provides a combined flat capacitor and TAB integrated circuit chip which reduces the power noise by using a bypass capacitor having an area smaller than the switching chip, thus allowing the positioning of the capacitor on top of the chip and decreasing the interconnect inductance. This can result in substantial real estate savings on high density multichip modules, for instance expensive copper/polyimide substrates in which over 50% of the surface area may be allocated to capacitors and resistors.